Dolby SR-D optical codes reverse engineering

This is a WIP.

Dolby SR-D was the second most popular sound-on-film technology, and arguably the most interesting. If you went to the movies in the 90's to the late 2000's, the sound you heard probably came from this thing.

This page will focus on the Dolby DA-20 electronics and its DSP software.
See this repo from David Ferguson for the history and links to documentation on the Dolby SR-D system as a whole.

Thanks to the creator of the Gugusse roller for providing a capture of raw codes.

 

DA-20 decoder teardown

Standard rack-mount decoder for SR-D tracks, evolution of the DA-10 and predecessor of the C650. Bought working from eBay for cheap.
Takes video of the scrolling codes with a fast Dalsa IL-C3-0512B 512 pixel linear CCD sensor (in the so-called soundhead) and outputs 6 analog audio channels along with some time markers and control signals for the cinema processor thing.
Installation and user manual available on film-tech.com. This website is AWESOME.

CAT. NO. 670

CCD control, analog video input, filtering, possible EQ/AGC, analog to digital conversion, small FIFO.

• MAX453: Dual-input multiplexer and video amplifier
• 1513-50A: Fixed delay line 50ohm 50ns (20MHz)
• AD829: High speed, low noise video amplifier
• OPA603: High speed, high voltage amplifier
• TL072: Double FET-input amplifier
• LM311: Comparator
• TL074: Quad FET-input amplifier
• 74LS628: VCO
• AS7C256: 32k * 8 SRAM
• Altera CPLDs
• DS26C31 / P9818: Quad differential line driver
• MP8785AN: 30MSPS 8-bit ADC

 

CAT. NO. 671

Two of these are used for a total of 4 video processing DSP blocks.

Video digital processing, data extraction from the 2D codes. Each DSP has the same small bootloader ROM to load programs from the master 673A board.
Each DSP has its own 128k x 24 of work RAM, which could hold 128k * 24 bits / 512 pixels / 8 bits per pixel = 768 lines from the CCD.

• DSP56001
• 27C512: 64k * 8 EPROM
• 74HC4538: Dual precision monostables (watchdogs ?)
• Altera CPLD
• AS7C1024: 128k * 8 SRAM
• 27C512 EPROM 84093 1.00 dump

Also 3x AS7C256: 32k * 8 SRAM, maybe input FIFOs ?

It is unverified but likely that all four DSPs are loaded with the same program, each processing one full code out of phase with each other to spread out the processing time.
A pipeline architecture where each DSP would perform a different processing step would mean lots of buffer memory multiplexing or wasteful data copying.

 

CAT. NO. 673A

Master controller, PLL for film speed tracking, Reed-Solomon EDC, uploading of programs to DSP boards, RS-232 external comm.

• DSP56002
• MX7245: 12-bit DAC
• VCO under a metal shield
• 29C010: 128k * 8 flash memory
• AS7C1024: 128k * 8 SRAM
• AS7C256: 32k * 8 SRAM
• AHA4011B: Reed-Solomon ERC ASIC
• 74HC4538: Dual precision monostables (watchdog ?)
• MAX232: Dual RS-232 driver/receiver
• 29C010 flash 84147 3.00 dump

 

CAT. NO. 675A

AC-3 decoding. The Zoran chip is one of their general-purpose DSPs but with embedded ROM for the Dolby decoding algorithm. Some small external ROM present, maybe for bootstraping.

• ZR38500: 6-channel AC-3 decoder
• PC16550: UART FIFO
• AS7C256: 32k * 8 SRAM
• 27C512 EPROM 84134 1.00 dump

 

CAT. NO. 686

Audio DACs for final output. Linear voltage regulators.

• CS4328: Dual 18-bit audio DAC
• NE5532: Dual low noise amplifier
• LM317T: Adjustable voltage regulator

 

CAT. NO. 611A

Cinema processor and user configuration interface, digital/analog audio switch. Audio level detection ?

• NE5532: Dual low noise amplifier
• AS7C256: 32k * 8 SRAM
• Motorola MCU
• MIC5801: 8-bit high voltage latch
• LM324: Quad op-amp
• MC33078: Dual high speed op-amp

 

2D code format

Dolby calls the transparent or opaque dots "fixels" for "film pixels".

Total: 76*76 fixels
Four 8*8 fixels corner markers (7-bit 2D Barker codes with border, probably to be located by autocorrelation)
A center 12*12 fixels logo
= 76*76 - 4*8*8 - 12*12 = 5776 - 400 = 5376 data bits per code

Four codes per frame at 24 frames per second:
4 * 24 * 5376 = 516096 bps = 504kbps = exactly 63kB/s

Bytes are packed in 2*4 fixel blocks, bit 0 top to bottom, left to right.

Raw ASCII data with no interleave: "DOLBY SR*D".

Special code every 44 codes = 11 frames = slightly less than half a second ?

Averaging 1900 contiguous codes, high entropy bytes marked in red:

Seems to be a 1:3 interleave of some sort on most of the data. Or are those EDC bytes ?

With the 512-pixel CCD, the highest sampling rate possible would be 512 / 76 = 6.73 sensor pixels per fixel.

Documentation say that synchronization is based on the light flashes caused by the sprocket holes between codes.
The flash frequency of 24 * 4 = 96Hz would need to be multiplied by at least 76 * 2 = 152 to reach the minimum line rate.

 

Firmware

Flash on 673A board contains all "applications" for the DSPs, seems to use a basic page / file system to allow fail-safe updates.

Stuck into IDA without knowing the memory map. Found the hard way that the entry point is at $4000, which isn't standard and doesn't match any startup mode of the DSP56002. So something on the PCB such as the Altera CPLD is mapping $4000 at $0000.

32kB bank switching done via the 2 lower bits of PORT D. Bank appears at $6000+.

Work RAM at $3900+, probably starts below.